LSYSTEM  Universal logic simulator V3 R2/10/1990  (c) P.Rushbrook & M.E. Brinson 
Compiler directives:
    .LIB filename              = Load primitive file. (must have at least 1)
    .INCLUDE filename          = Include text/MACRO file.
    .MACRO name N1 N2 .... NN  = Macro definition start.
    .ENDM                      = End of macro definition.
    .SUBCKT .... .ENDS         = Same as .MACRO .... .ENDM.
    .LIST                      = Produce listing (.LST) file.
    .EXPAND                    = Produce listing with macro expansion (.EXP).
    .END                       = End of circuit description file.
    .PRINT N1 N2 .... NN       = Output node table  to result file (.RLT).
    .PLOT  N1 N2 .... NN       = Output node plot to result file (.RLT).
    .TIME TFIN WD_time_int
Element syntax.
    Element_name node1 node2 ..... PRIMITIVE/MACRO_name <option, option, ....>
    Options: delay(nS), rise(nS), fall(nS), strength(%), high(%), low(%).
Clock syntax.
    (1) Element_name node CLK0 | CLK1 T1 T2 T3 ...... TN
    (2) Element_name node CLK0 | CLK1 PERIOD(TP)
    (3) Element_name node CLK0 | CLK1 REPEAT(TD NOR T1 T2 T3 T4 ...... TF)
    (4) Element_name node CLK0 | CLK1 TABLE(TD Tinc 0,1,1,1,.............)
<<<<<<<<<<<<  All times are in nS.   CLK0 | CLK1 means CLK0 or CLK1.  >>>>>>>>>>